1. Field of the Invention
The present invention relates to an input circuit of a semiconductor integrated circuit device, and more particularly, to a technique for improving the reliability of an input circuit which receives an input voltage which is higher than a power source voltage which is applied to the input circuit.
2. Description of the Prior Art
Due to recent development in the semiconductor technology, a MOS semiconductor integrated circuit device has increasingly high-component-density. As a result, in a MOS semiconductor integrated circuit device of fine structure, the thickness of agate insulation film is extremely thin, 10 nm to 14 nm. Hence, in order to prevent dielectric breakdown of the gate insulation film and to prevent a variation in a threshold voltage of a MOS transistor due to fixed charges in the gate insulation film which are created by hot electrons which are created during the operative state of the MOS transistor and implanted into the gate insulation film, a power source voltage to be applied to the fine MOS semiconductor integrated circuit device is set lower than a power source voltage which is applied to a conventional MOS semiconductor integrated circuit device. In general, an output voltage of a MOS semiconductor integrated circuit device is equal to a potential difference between a power source potential V.sub.DD1 and a ground potential V.sub.SS. Although in most cases the voltage of an input signal which is given to an input circuit is equal to a power source voltage for operating the input circuit, in data transmission between semiconductor integrated circuit devices 50 and 51 which operate at different power source voltages (e.g., 3.3 V and 5 V) as shown in FIG. 5, a binary signal which is outputted from the semiconductor integrated circuit device 51 to the semiconductor integrated circuit device 50, for example, is around 0 V (L level) and 5 V (H level) in general. Hence, in applying an output signal of the semiconductor integrated circuit device 51 which operates at a voltage which is higher than a power source voltage for the MOS semiconductor integrated circuit device 50 having fine features, for instance, to the MOS semiconductor integrated circuit device 50 of fine geometry, a voltage V.sub.GP which can be applied to a gate electrode of a P channel MOS transistor must be in the range V.sub.SS .ltoreq.V.sub.GP .ltoreq.2.times.V.sub.DD1 while a voltage V.sub.GN which can be applied to agate electrode of an N channel MOS transistor must be in the range V.sub.SS .ltoreq.V.sub.GN .ltoreq.V.sub.DD1.
This is an important consideration fir an input circuit of a semiconductor integrated circuit device. In other words, to obtain an input circuit which is sufficiently reliable, in the case where as an input circuit, an invertor is used which is formed by a P channel MOS transistor having a backgate potential which is fixed to the power source potential V.sub.DD1 and an N channel MOS transistor having a backgate potential which is fixed to the ground potential V.sub.SS, for example, the voltage V.sub.GP which can be applied to the gate electrode of the P channel MOS transistor and the voltage V.sub.GN which can be applied to the gate electrode of the N channel MOS transistor must be in the respective ranges above.
FIG. 6 is a circuitry diagram of a conventional input circuit of a semiconductor integrated circuit device. In FIG. 6, Tr5 is a P channel MOS transistor and Tr6 is an N channel MOS transistor. Indicated at reference numeral 1 is a power source which serves as a first potential point to which the power source potential V.sub.DD1 is applied, indicated at reference numeral 2 is a ground which serves as a second potential point to which the ground potential V.sub.SS is applied, indicated at reference numeral 3 is an input terminal of the input circuit, and indicated at reference numeral 4 is an output terminal of the input circuit.
Next, operations of the conventional input circuit will be described. A substrate of the P channel MOS transistor Tr5 is connected to the power source 1 so that the backgate potential of the P channel MOS transistor Tr5 is fixed at the power source potential V.sub.DD1. A substrate of the N channel MOS transistor Tr6 is grounded so that the backgate potential of the N channel MOS transistor Tr6 is fixed at the ground potential V.sub.SS. The P channel MOS transistor Tr5 and the N channel MOS transistor Tr6 form a CMOS invertor circuit, and therefore, if the voltage V.sub.IN of a signal which is applied to the input signal terminal 3 satisfies V.sub.T .ltoreq.V.sub.IN where a logical threshold voltage of the CMOS invertor circuit is V.sub.T, the power source potential V.sub.DD1 which is available from the power source 1 is outputted at the output terminal 4 of the input circuit. On the other hand, if V.sub.IN .ltoreq.V.sub.T, the ground potential V.sub.SS which is supplied from the ground 2 is outputted at the output terminal 4 of the input circuit.
Now, description will be given with reference to FIG. 7 on voltages which will be applied to the gate insulation films of the P channel MOS transistor Tr5 and the N channel MOS transistor Tr6 when the output V.sub.IN of the semiconductor into, grated circuit device 51 is received by the input circuit shown in FIG. 6 which is mounted in the semiconductor integrated circuit device 50.
In the P channel MOS transistor Tr5, since the backgate potential is V.sub.DD1 when the input signal V.sub.DD1 is at L level, the voltage V.sub.G which is applied to the gate insulation film of the P channel MOS transistor Tr5 is -V.sub.DD1 with respect to a potential at the source electrode. As the input voltage V.sub.IN changes from L level to H level, the gate voltage at the P channel MOS transistor Tr5 increases accordingly. When the input voltage V.sub.IN has risen to H level, a voltage applied to the gate insulation film of the P channel MOS transistor Tr5 amounts to 1.7 V.
In the N channel MOS transistor Tr6, when the input signal V.sub.IN is at L level, the backgate potential of the N channel MOS transistor Tr6 is V.sub.SS. Hence, a voltage which is applied to the gate insulation film of the N channel MOS transistor Tr6 is 0 V with respect to a potential at the source electrode. As the input voltage V.sub.IN changes from L level to H level, the gate voltage at the N channel MOS transistor Tr6 increases accordingly. When the input voltage V.sub.IN has risen to H level, a voltage which is applied to the gate insulation film of the N channel MOS transistor Tr6 amounts to the power source voltage V.sub.DD2 for the semiconductor integrated circuit device 51 shown in FIG. 5 (i.e., 5 V). Thus, a voltage exceeding V.sub.DD1 is applied to the gate electrode of the N channel MOS transistor Tr6, degrading the reliability of the input circuit.
A relation between a gate electrode and a semiconductor substrate will be explained with reference to FIG. 8 which shows a cross section of an invertor which is formed on a semiconductor substrate. In FIG. 8, indicated at reference numeral 60 is the semiconductor substrate, indicated at reference numeral 61 is a p-well which is formed on the semiconductor substrate 60, indicated at reference numeral 62 is an n-well which is formed on the semiconductor substrate 60, indicated at reference numeral 63 is a p.sup.+ buried region which is formed on the p-well 61, indicated at reference numeral 64 is a source electrode of an N channel MOS transistor which is formed on the p-well 61, indicated at reference numeral 65 is a drain electrode of the N channel MOS transistor which is formed on the p-well 61, indicated at reference numeral 69 is a gate electrode of the N channel MOS transistor, indicated at reference numeral 69a is a gate insulation film of the gate electrode 69, indicated at reference numeral 66 is a drain electrode of a P channel MOS transistor which is formed on the n-well 62, indicated at reference numeral 67 is a source electrode of the P channel MOS transistor which is formed on the n-well 62, indicated at reference numeral 68 is an n.sup.+ buried region which is formed on the n-well 62, indicated at reference numeral 70 is a gate electrode of the P channel MOS transistor, and indicated at reference numeral 70a is a gate insulation film of the gate electrode 70. The source electrode 64 of the N channel MOS transistor and the p.sup.+ buried region 63 are grounded to stay at the ground potential V.sub.SS so that the backgate potential of the N channel MOS transistor is fixed at V.sub.SS. On the other hand, the source electrode 67 of the P channel MOS transistor and the buried region 68 are connected to the power source 1 to remain at the power source potential V.sub.DD1 so that the backgate potential of the P channel MOS transistor is fixed at V.sub.DD1. The gate electrodes of the N channel MOS transistor and the P channel MOS transistor are connected to the input terminal 3 while the drain electrode 65 of the N channel MOS transistor and the drain electrode 66 of the P channel MOS transistor are connected to the output terminal 4. Hence, a voltage which is applied to the gate insulation films 69a and 70a is equal to a difference between the associated backgate potential and a potential at the input terminal 3.
Since the conventional input circuit of a semiconductor integrated circuit device has such a structure, when the voltage of the input signal V.sub.IN is larger than the power source voltage V.sub.DD1 tier the semiconductor integrated circuit device 50 as shown in FIG. 5, an excessively large voltage is applied to the gate insulation film of the N channel MOS transistor Tr6. This causes various reliability related problems such as destruction of the insulation film and shortened operating life of the MOSFET.